AMD Athlon x4 950 Firmware vulnerabilities

7 CVEs affecting AMD Athlon x4 950 Firmware, 0 known to be exploited (CISA KEV), with EPSS scores. Latest: CVE-2022-27672, published 2023-03-01.

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Known exploited (CISA KEV) first, then by EPSS exploit probability.

• CVE-2022-29900, published 2022-07-12. Medium severity, CVSS 6.5. EPSS: 3.9% chance of exploitation in the next 30 days. Mis-trained branch predictions for return instructions may allow arbitrary speculative code execution under certain microarchitecture-dependent conditions.
• CVE-2022-23823, published 2022-06-15. Medium severity, CVSS 6.5. EPSS: 1.2% chance of exploitation in the next 30 days. A potential vulnerability in some AMD processors using frequency scaling may allow an authenticated attacker to execute a timing attack to potentially enable information disclosure.
• CVE-2022-23825, published 2022-07-14. Medium severity, CVSS 6.5. EPSS: 0.8% chance of exploitation in the next 30 days. Aliases in the branch predictor may cause some AMD processors to predict the wrong branch type potentially leading to information disclosure.
• CVE-2022-23824, published 2022-11-09. Medium severity, CVSS 5.5. EPSS: 0.6% chance of exploitation in the next 30 days. IBPB may not prevent return branch predictions from being specified by pre-IBPB branch targets leading to a potential information disclosure.
• CVE-2021-26341, published 2022-03-11. Medium severity, CVSS 6.5. EPSS: 0.3% chance of exploitation in the next 30 days. Some AMD CPUs may transiently execute beyond unconditional direct branches, which may potentially result in data leakage.
• CVE-2021-26401, published 2022-03-11. Medium severity, CVSS 5.6. EPSS: 0.3% chance of exploitation in the next 30 days. LFENCE/JMP (mitigation V2-2) may not sufficiently mitigate CVE-2017-5715 on some AMD CPUs.
• CVE-2022-27672, published 2023-03-01. Medium severity, CVSS 4.7. EPSS: 0.3% chance of exploitation in the next 30 days. When SMT is enabled, certain AMD processors may speculatively execute instructions using a target from the sibling thread after an SMT mode switch potentially resulting in information disclosure.